The present invention relates generally to field effect transistor fabrication, and most particularly to engineering of the channel under the transistor to counter short field effects in deep-submicron complementary (CMOS) field effect transistors on the same chip.
When MOSFET gate length is scaled below 100 nanometers (nm), short channel effects become significant factors. Strong or higher implant dose halo implants are widely used in deep submicron CMOS technology to engineer the FET channel to overcome short channel effects. Strong halo implants however, tend to degrade channel mobility, resulting in low device drive current. The usual single halo implant is not sufficient to control threshold voltage (Vth) roll-off at approximately 50 nm gate lengths or smaller. What is needed is a method to engineer the channel doping profile to overcome the short channel effects in deep submicron CMOS chips having gate lengths of approximately 50 nm or less.
The present invention is a method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. By way of example, and not of limitation, the method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of approximately 50 nm or less. The method involves a deep source/drain implant and anneal, followed by an angled deep halo implant and a second annealing at a temperature lower than the first anneal. An amorphization implant is then made, followed by a second angled halo implant, formation of source/drain extensions and a third anneal at a temperature less than the second anneal. The microelectronic chip is then silicided and the MOSFET is further completed.
The resultant device operates at an increased speed compared to similar heretofore known devices. The instant method improves device density on the substrate and improves manufacturing precision and efficiency. Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.